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[n]	K. T. Hsu, K. H. Hu, C. H. Kuo, W. K. Lau, C. J. Wang, and M. S. Yeh, “Architecture of Longitudinal Feedback Software System in TLS”, in Proc. EPAC'00, Vienna, Austria, Jun. 2000, paper WEP2B03, pp. 1915-1917. 

[n]	D. Dom?¡nguez, J. J. Gras, J. Lewis, J. J. Savioz, J. Serrano, and F. J. Ballester, “An FPGA Based Multiprocessing CPU for Beam Synchronous Timing in CERN's SPS and LHC”, in Proc. ICALEPCS'03, Gyeongju, Korea, Oct. 2003, paper MP531, pp. 113-115. 

For LaTeX

%\cite{Hsu:EPAC00-WEP2B03} \bibitem{Hsu:EPAC00-WEP2B03} K. T. Hsu, K. H. Hu, C. H. Kuo, W. K. Lau, C. J. Wang, and M. S. Yeh, \textquotedblleft{Architecture of Longitudinal Feedback Software System in TLS}\textquotedblright, in \emph{Proc. EPAC’00}, Vienna, Austria, Jun. 2000, paper WEP2B03, pp. 1915--1917. %\cite{Dom?¡nguez:ICALEPCS03-MP531} \bibitem{Dom?¡nguez:ICALEPCS03-MP531} D. Dom?¡nguez, J. J. Gras, J. Lewis, J. J. Savioz, J. Serrano, and F. J. Ballester, \textquotedblleft{An FPGA Based Multiprocessing CPU for Beam Synchronous Timing in CERN's SPS and LHC}\textquotedblright, in \emph{Proc. ICALEPCS’03}, Gyeongju, Korea, Oct. 2003, paper MP531, pp. 113--115.

For BibTeX

@inproceedings{hsu:epac00-wep2b03, author = {K. T. Hsu and K. H. Hu and C. H. Kuo and W. K. Lau and C. J. Wang and M. S. Yeh}, title = {{Architecture of Longitudinal Feedback Software System in TLS}}, booktitle = {Proc. EPAC'00}, pages = {1915--1917}, paper = {WEP2B03}, venue = {Vienna, Austria}, series = {European Particle Accelerator Conference}, number = {7}, publisher = {JACoW Publishing, Geneva, Switzerland}, month = {8}, year = {2000}, url = {https://jacow.org/e00/papers/WEP2B03.pdf}, language = {english} } @inproceedings{dom?¡nguez:icalepcs03-mp531, author = {D. Dom?¡nguez and J. J. Gras and J. Lewis and J. J. Savioz and J. Serrano and F. J. Ballester}, title = {{An FPGA Based Multiprocessing CPU for Beam Synchronous Timing in CERN's SPS and LHC}}, booktitle = {Proc. ICALEPCS'03}, pages = {113--115}, paper = {MP531}, venue = {Gyeongju, Korea, Oct. 2003}, publisher = {JACoW Publishing, Geneva, Switzerland}, url = {https://jacow.org/ica03/papers/MP531.pdf}, language = {english} }

References

• K. T. Hsu, K. H. Hu, C. H. Kuo, W. K. Lau, C. J. Wang, and M. S. Yeh, “Architecture of Longitudinal Feedback Software System in TLS”, in Proc. 7th European Particle Accelerator Conf. (EPAC'00), Vienna, Austria, Jun. 2000, paper WEP2B03, pp. 1915-1917.
• D. Dom?¡nguez, J. J. Gras, J. Lewis, J. J. Savioz, J. Serrano, and F. J. Ballester, “An FPGA Based Multiprocessing CPU for Beam Synchronous Timing in CERN's SPS and LHC”, in Proc. 9th Int. Conf. on Accelerator and Large Experimental Physics Control Systems (ICALEPCS'03), Gyeongju, Korea, Oct. 2003, paper MP531, pp. 113-115.