[n] K. Nishiyama et al., “FPGA Utilization in the Accelerator Interlock System (About the MPS Development in the LIPAc)”, in Proc. PCaPAC'14, Karlsruhe, Germany, Oct. 2014, paper FPO019, pp. 201-203.
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Paper Title: FPGA Utilization in the Accelerator Interlock System (About the MPS Development in the LIPAc)
Paper URL: https://jacow.org/PCaPAC2014/papers/FPO019.pdf
Conference: 10th Int. Workshop on Personal Computers and Particle Accelerator Controls (PCaPAC'14)
Paper ID: FPO019
Location in proceedings: 201-203
Original Author String: K. Nishiyama [Japan Atomic Energy Agency (JAEA), International Fusion Energy Research Center (IFERC), Rokkasho, Kamikita, Aomori, Japan] R. Gobin [CEA/IRFU, Gif-sur-Yvette, France] J. Knaster, A. Marqueta Barbero, Y. Okumura [IFMIF/EVEDA, Rokkasho, Japan] T. Kojima, T. Narita, H. Sakaki, H. Takahashi [JAEA, Aomori, Japan]
