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[n]	D. Dom?¡nguez, J. J. Gras, J. Lewis, J. J. Savioz, J. Serrano, and F. J. Ballester, “An FPGA Based Multiprocessing CPU for Beam Synchronous Timing in CERN's SPS and LHC”, in Proc. ICALEPCS'03, Gyeongju, Korea, Oct. 2003, paper MP531, pp. 113-115. 

For LaTeX

%\cite{Dom?¡nguez:ICALEPCS03-MP531} \bibitem{Dom?¡nguez:ICALEPCS03-MP531} D. Dom?¡nguez, J. J. Gras, J. Lewis, J. J. Savioz, J. Serrano, and F. J. Ballester, \textquotedblleft{An FPGA Based Multiprocessing CPU for Beam Synchronous Timing in CERN's SPS and LHC}\textquotedblright, in \emph{Proc. ICALEPCS’03}, Gyeongju, Korea, Oct. 2003, paper MP531, pp. 113--115.

For BibTeX

@inproceedings{dom?¡nguez:icalepcs03-mp531, author = {D. Dom?¡nguez and J. J. Gras and J. Lewis and J. J. Savioz and J. Serrano and F. J. Ballester}, title = {{An FPGA Based Multiprocessing CPU for Beam Synchronous Timing in CERN's SPS and LHC}}, booktitle = {Proc. ICALEPCS'03}, pages = {113--115}, paper = {MP531}, venue = {Gyeongju, Korea, Oct. 2003}, publisher = {JACoW Publishing, Geneva, Switzerland}, url = {https://jacow.org/ica03/papers/MP531.pdf}, language = {english} }

References

• D. Dom?¡nguez, J. J. Gras, J. Lewis, J. J. Savioz, J. Serrano, and F. J. Ballester, “An FPGA Based Multiprocessing CPU for Beam Synchronous Timing in CERN's SPS and LHC”, in Proc. 9th Int. Conf. on Accelerator and Large Experimental Physics Control Systems (ICALEPCS'03), Gyeongju, Korea, Oct. 2003, paper MP531, pp. 113-115.