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[n] J.-Y. Chuang, C.-C. Chang, C. M. Cheng, Y. Z. Lin, I. C. Sheng, and Y. C. Yang, “The Development of a FPGA Based Front End Safety Interlock System”, in Proc. PCaPAC'18, Hsinchu City, Taiwan, Oct. 2018, pp. 189-191. doi:10.18429/JACoW-PCaPAC2018-THP13
[n] K. Akai, N. Akasaka, K. Ebihara, E. Ezura, M. Suetake, and S. Yoshimoto, “The Low-Level RF System for KEKB”, in Proc. EPAC'98, Stockholm, Sweden, Jun. 1998, paper TUP10G, pp. 1749-1751.
[n] G. Joshi, V. Agarwal, G. Kumar, and R. G. Pillay, “Development of the Model of a Self Excited Loop”, in Proc. PAC'09, Vancouver, Canada, May 2009, paper WE3RAC06, pp. 1886-1888.
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References
- J.-Y. Chuang, C.-C. Chang, C. M. Cheng, Y. Z. Lin, I. C. Sheng, and Y. C. Yang, “The Development of a FPGA Based Front End Safety Interlock System”, in Proc. 12th International Workshop on Personal Computers and Particle Accelerator Controls (PCaPAC'18), Hsinchu City, Taiwan, Oct. 2018, pp. 189-191.
- K. Akai, N. Akasaka, K. Ebihara, E. Ezura, M. Suetake, and S. Yoshimoto, “The Low-Level RF System for KEKB”, in Proc. 6th European Particle Accelerator Conf. (EPAC'98), Stockholm, Sweden, Jun. 1998, paper TUP10G, pp. 1749-1751.
- G. Joshi, V. Agarwal, G. Kumar, and R. G. Pillay, “Development of the Model of a Self Excited Loop”, in Proc. 23rd Particle Accelerator Conf. (PAC'09), Vancouver, Canada, May 2009, paper WE3RAC06, pp. 1886-1888.
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