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[n]	D. Dom?¡nguez, J. J. Gras, J. Lewis, J. J. Savioz, J. Serrano, and F. J. Ballester, “An FPGA Based Multiprocessing CPU for Beam Synchronous Timing in CERN's SPS and LHC”, in Proc. ICALEPCS'03, Gyeongju, Korea, Oct. 2003, paper MP531, pp. 113-115. 

[n]	E. P. Chojnacki et al., “Design of an ERL Linac Cryomodule”, in Proc. PAC'09, Vancouver, Canada, May 2009, paper WE6RFP002, pp. 2781-2783. 

For LaTeX

%\cite{Dom?¡nguez:ICALEPCS03-MP531} \bibitem{Dom?¡nguez:ICALEPCS03-MP531} D. Dom?¡nguez, J. J. Gras, J. Lewis, J. J. Savioz, J. Serrano, and F. J. Ballester, \textquotedblleft{An FPGA Based Multiprocessing CPU for Beam Synchronous Timing in CERN's SPS and LHC}\textquotedblright, in \emph{Proc. ICALEPCS’03}, Gyeongju, Korea, Oct. 2003, paper MP531, pp. 113--115. %\cite{Chojnacki:PAC09-WE6RFP002} \bibitem{Chojnacki:PAC09-WE6RFP002} E. P. Chojnacki \emph{et al.}, \textquotedblleft{Design of an ERL Linac Cryomodule}\textquotedblright, in \emph{Proc. PAC’09}, Vancouver, Canada, May 2009, paper WE6RFP002, pp. 2781--2783.

For BibTeX

@inproceedings{dom?¡nguez:icalepcs03-mp531, author = {D. Dom?¡nguez and J. J. Gras and J. Lewis and J. J. Savioz and J. Serrano and F. J. Ballester}, title = {{An FPGA Based Multiprocessing CPU for Beam Synchronous Timing in CERN's SPS and LHC}}, booktitle = {Proc. ICALEPCS'03}, pages = {113--115}, paper = {MP531}, venue = {Gyeongju, Korea, Oct. 2003}, publisher = {JACoW Publishing, Geneva, Switzerland}, url = {https://jacow.org/ica03/papers/MP531.pdf}, language = {english} } @inproceedings{chojnacki:pac09-we6rfp002, author = {E. P. Chojnacki and others}, title = {{Design of an ERL Linac Cryomodule}}, booktitle = {Proc. PAC'09}, pages = {2781--2783}, paper = {WE6RFP002}, venue = {Vancouver, Canada, May 2009}, series = {Particle Accelerator Conference}, number = {23}, publisher = {JACoW Publishing, Geneva, Switzerland}, url = {https://jacow.org/PAC2009/papers/WE6RFP002.pdf}, language = {english} }

References

• D. Dom?¡nguez, J. J. Gras, J. Lewis, J. J. Savioz, J. Serrano, and F. J. Ballester, “An FPGA Based Multiprocessing CPU for Beam Synchronous Timing in CERN's SPS and LHC”, in Proc. 9th Int. Conf. on Accelerator and Large Experimental Physics Control Systems (ICALEPCS'03), Gyeongju, Korea, Oct. 2003, paper MP531, pp. 113-115.
• E. P. Chojnacki et al., “Design of an ERL Linac Cryomodule”, in Proc. 23rd Particle Accelerator Conf. (PAC'09), Vancouver, Canada, May 2009, paper WE6RFP002, pp. 2781-2783.