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[n]	P. Bachek, G. Narayan, K. Mernick, M. Costanzo, and S. Mai, “Design of a standardized FPGA architecture for EIC common platform daughtercards”, in Proc. ICALEPCS'25, Chicago, IL, USA, Sep. 2025, pp. 213-216. doi:10.18429/JACoW-ICALEPCS2025-MODR007

For LaTeX

%\cite{Bachek:ICALEPCS25-MODR007} \bibitem{Bachek:ICALEPCS25-MODR007} P. Bachek, G. Narayan, K. Mernick, M. Costanzo, and S. Mai, \textquotedblleft{Design of a standardized FPGA architecture for EIC common platform daughtercards}\textquotedblright, in \emph{Proc. ICALEPCS’25}, Chicago, IL, USA, Sep. 2025, pp. 213--216. \doi{10.18429/JACoW-ICALEPCS2025-MODR007}

For BibTeX

@inproceedings{bachek:icalepcs25-modr007, author = {P. Bachek and G. Narayan and K. Mernick and M. Costanzo and S. Mai}, title = {{Design of a standardized FPGA architecture for EIC common platform daughtercards}}, booktitle = {Proc. ICALEPCS'25}, pages = {213--216}, paper = {MODR007}, venue = {Chicago, IL, USA}, series = {Int. Conf. on Accelerator and Large Experimental Physics Control Systems}, number = {20}, publisher = {JACoW Publishing, Geneva, Switzerland}, month = {12}, year = {2025}, issn = {2226-0358}, isbn = {978-3-95-450255-4}, doi = {10.18429/JACoW-ICALEPCS2025-MODR007}, language = {english} }

References

• P. Bachek, G. Narayan, K. Mernick, M. Costanzo, and S. Mai, “Design of a standardized FPGA architecture for EIC common platform daughtercards”, in Proc. 20th International Conference on Accelerator and Large Experimental Control Systems (ICALEPCS'25), Chicago, IL, USA, Sep. 2025, pp. 213-216.